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DATA SHEET
MICRONAS
UAC 3553B Universal Serial Bus (USB) DAC
Edition Feb. 17, 2005 6251-595-2DS
MICRONAS
UAC 3553B
Contents Page 4 4 6 7 7 7 7 7 7 7 8 8 8 8 8 9 9 9 9 10 10 10 10 10 11 11 11 11 11 11 12 13 13 13 13 13 14 14 14 15 15 Section 1. 1.1. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.3. 2.4. 2.5. 2.6. 2.7. 2.7.1. 2.7.2. 2.8. 2.9. 2.9.1. 2.9.2. 2.10. 2.10.1. 2.10.2. 2.10.3. 2.10.4. 2.11. 2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.12. 3. 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.8. 3.8.1. 3.8.2. Title Introduction Features Hardware Description General Information Universal Serial Bus (USB) Transceiver USB Interface Microcontroller GPIO General-Purpose Timer Audio Streaming Interface Audio Control Interface I2S Interface Asynchronous I2S input Synchronous I2S Input Mode Power Supply I2C Bus Interface I2C Master I2C Slave Analog Output Digital-to-Analog Converters Analog Filter Analog Volume Line-out/Headphone Amplifier Special I/O SOF (Start of Frame) SEN (Suspend Enable) Suspend Reset Clock System Audio Processing Sample Rate Converters Automatic Gain Control Quasi-Peak Bass Control Treble Control Parametric Equalizer Volume, Mute, and Balance Control Micronas Bass (MB) Dynamic Amplification Adding Harmonics
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Contents, continued Page 16 16 16 16 17 18 18 19 19 20 22 22 22 23 23 24 25 27 27 29 31 36 38 38 38 39 40 Section 4. 4.1. 4.1.1. 4.1.2. 4.1.3. 4.2. 4.2.1. 5. 5.1. 5.2. 5.3. 5.3.1. 5.3.2. 5.3.3. 5.3.4. 5.4. 5.5. 5.6. 5.6.1. 5.6.2. 5.6.3. 5.6.4. 6. 6.1. 6.2. 6.3. 7. Title Firmware Features Device Descriptor Configuration Descriptor Audio Class Requests Vendor-Specific Requests Bootloader Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Audio Pins Interface Pins Other Pins Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics I2S Interface Timing Characteristics UAC 3553B Applications Recommended Low-Pass Filters for Analog Outputs External Clocking via XTI Typical Application Data Sheet History
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UAC 3553B
Universal Serial Bus (USB) DAC
DATA SHEET
Table 1-1: Members of the UAC 355xB family Version Description USB DAC USB headset USB codec USB codec-emulator version with additional 8 k RAM for program download.
Release Note: Revision bars indicate significant changes to the previous edition.
UAC 3553B UAC 3554B
1. Introduction The UAC 3553B is a fully integrated 2-channel audio digital-to-analog converter (DAC) with an integrated USB 2.0 full-speed interface controller. The device offers audio processing such as volume, bass, and treble. Furthermore, the UAC 3553B integrates a programmable 5-band parametric equalizer for correcting the frequency response of the applied speakers. Integrated headphone amplifiers allow direct headphone connection. The DAC is driven by digital audio input via a USB Audio Class-compliant isochronous stream 16 or 24 bits wide or via an I2S input 16 or 32 bits wide. Both audio input data can be fully mixed to the DAC output. The integrated high-quality DSP-based adaptive sample rate converter accepts USB audio streams in a wide range from 6.4 to 48 KHz. General-purpose inputs and outputs connect the UAC 3553B to peripheral hardware such as buttons, keyboards, LEDs, etc. USB HID Device class for audio controls is supported. Over an I2C master, more complex peripherals, such as LCD displays can be controlled; and the UAC 3553B itself can be remote-controlled via I2C slave operation. This allows communication pipelining between a peripheral I2C system controller and the USB host. All-in-all, the IC is designed as the ideal connecting matrix between USB, digital audio input, home stereo, and all kinds of human interface devices. Many functions are adjustable to the customer's needs. Moreover, firmware customizing and plug-in download functionality to the on-chip microcontroller turns the UAC 3553B into a customer-specific IC. Micronas supplies a standard ROM firmware based on the USB Composite Class, Audio Class, and HID Class.
UAC 3555B UAC 3556B
1.1. Features - single-chip, USB specification 2.0 compliant, stereo audio D/A converter - supports up to 24-bit playback - optional vendor identification and device configuration with external EEPROM - bus-powered and self-powered mode possible - remote wake-up - 8 general-purpose input/output pins with HID support - I2S input interface - independent adaptive sample rates of 6.4 to 48 kHz for USB playback - audio baseband control: bass, treble, loudness, volume, balance, and mute - dynamic bass management Micronas Bass (MB) - digital speaker equalizer (5-band parametric equalizer) - THD better than -90 dB and SNR of typical 96 dB for D/A converters - power supply rejection ratio >95 dB for analog outputs - integrated stereo headphone amplifier - I2C interface (master/slave) - customized firmware extensions possible with plugins
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HID and GPIO
I 2C
I 2S
D+ USB Controlling D-
Audio Processing Unit (APU)
DAC
Volume Volume and and Headphone Headphone Amplifier Amplifier
OUTL OUTR
ROM RAM
Fig. 1-1: Block diagram of the UAC 3553B
Active Stereo Speakers
USB
UAC 3553B
Headphone
Stereo Equipment Fig. 1-2: System application diagram
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2. Hardware Description
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VBUS
D-
D+
Transceiver Volt. Reg. USB Interface
SOF
VREG
MicroController
GPI/O
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 TEST
XTI
XTO
Oscillator + PLL
Audio Control Interface
Audio Streaming Interface
Control I/O
TRDY RES SUSPEND SEN
I2C
SCL SDA
DAI
Audio Processing Unit (APU)
I2S
WSI CLI
DAC
VDD VSS AVDD AREG0 AREG1 AVSS0/1
FOPR FOUTR
Supply Voltage Reg. Reference
Analog Filter
FINR FOPL FOUTL
Analog Volume
FINL
SGND SREF
Headphone Amplifier
OUTL
OUTR
Fig. 2-1: Detailed block diagram of the UAC 3553B
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as a patch area. One example is adding extra functions to the GPIO pins, like control of external components via USB. Downloading of the plug-in can be done either from the USB host with an extra driver or from an external I2C EEPROM.
2.1. General Information This description summarizes all hardware platform capabilities of the UAC 3553B. The functionality for a certain application, however, is defined in the microcontroller's firmware. This is explained in Section 4. "Firmware" on page 16. The basic functions (playback, audio control, HID) of the UAC 3553B can entirely be used by any USB operating system without additional drivers. However, the IC offers far more functions if vendorspecific controlling or download code is used. With external I2C controlling, the IC can even work as an audio DAC in a non-USB environment. The use of this complete functionality is not described in the standard data sheet and can be found in separate application notes (www.micronas.com). A detailed block diagram of the UAC 3553B is depicted in Fig. 2-1. The functions of the blocks are explained in the following sections.
2.3. GPIO The pins GPIO0...GPIO7 can be switched into different electrical states: - input, output, or tristate - weak or strong driver strength - internal pull-down on or off
2.4. General-Purpose Timer The UAC 3553B incorporates a timer. It is a 16-bit counter with clock prescaler. The clock runs at 12 MHz. The prescaler can be set to divide by 1 to 256. The current value of the counter can always be read back. The timer initiates interrupts on reaching the count value MaxA. The structure of the timer is shown in Fig. 2-2. Timer frequency:
12MHz - T CLK = ---------------------- Prescale
2.2. Universal Serial Bus (USB) 2.2.1. Transceiver The differential input transceiver is used to handle the USB data signal according to the full-speed (12 MB/s) USB driver characteristics (USB SPEC 2.0). This block is supplied by an internal voltage regulator. The internal pull-up resistor on the D+ line, indicating that the UAC 3553B is connected to the USB bus, can be switched on and off by firmware.
2.2.2. USB Interface The USB interface does all the low-level USB protocol handling, like NRZI coding, bit-stuffing and CRC computation. A receiver/transceiver logic handles the data traffic between the USB bus and the microcontroller memory.
Timer Interrupt
Control
2.2.3. Microcontroller The microcontroller is an 8-bit RISC controller which handles the USB Chapter-9 processing and the decoding of class and vendor-specific USB requests. Detailed information is available in a separate document. The basic configuration is: - 2 KB RAM - 12 KB ROM A part of the RAM is reserved for download plug-ins. This allows the addition of smaller portions of code to the basic firmware for extended functionality or serves
Max A Max B Tclk Prescaler Counter
12 MHz
Fig. 2-2: Timer structure
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2.5. Audio Streaming Interface The audio streaming interface directly connects the USB interface to the APU in order to transmit the digital audio data for playback. The following data formats are supported: Table 2-1: Audio formats Playback 16-bit MONO 16-bit STEREO 24-bit STEREO UAC 3553B DAI CLI WSI 2.7.1. Asynchronous I2S input Used Pins: DAI, WSI, CLI
DATA SHEET
In this mode the UAC 3553B is slave, i.e., asynchronous input is possible at a sampling rate range from 6.4 kHz to 48 kHz. The external I2S source provides DAI, WSI, and CLI
asynchronous input
2.6. Audio Control Interface The audio control interface links the microcontroller to the APU and is used to initialize the APU and to transmit audio-related USB control data, such as volume setting, tone control, etc.
Fig. 2-3: Asynchronous I2S input The audio control interface provides full access to all APU registers via the microcontroller. 2.7.2. Synchronous I2S Input Mode 2.7. I2S Interface Used Pins: DAI, WSI, CLI The I2S interfaces operate in 16-bit or 32-bit mode. Delayed word strobe or standard I2S format can be selected via programmable delay bit. Word strobe polarity is also programmable. Used Pins: DAO, DAI, WSI, CLI In this mode external digital sources use CLI and WSI as reference and generate synchronous input data on DAI.
UAC 3553B
DAI CLI WSI synchronous input
Fig. 2-4: Synchronous I2S input
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2.9. I2C Bus Interface Pins: SDA, SCL The UAC 3553B is equipped with an I2C bus master/ slave interface. The bus format and timing follows the original specification for I2C (The I2C Specification V2.1). It operates with 5 V signaling at 100 kHz or 400 kHz. Both master and slave mode require support from the microcontroller firmware.
2.8. Power Supply The UAC 3553B has on-chip voltage regulators providing the optimal supply voltages for the analog and digital sections, thus allowing to power the IC by the USB bus supply lines, as well as from external supply. They are also used to reduce cross-talk and EMI. For stable operation, all regulators need external capacitors.
The regulators are 1. VREG: 3.4 V Regulator for USB signalling (saving external regulator) 2. AREG0: 3.5 V regulator for analog back-end 3. AREG1: 3.5 V regulator for analog circuitry apart from backend. 2.9.1. I2C Master This mode allows control of external I2C devices, such as EEPROMs, LCD-Displays etc. This interface is used to download configuration data and firmware from an EEPROM after power-up. The bus protocol (subaddressing and packet length) is defined by firmware, and so is programmable.
Reference voltage for analog signals: SREF: 1.7 V (optional 2.3 V) reference voltage for analog circuitry.
Note: Micronas standard firmware (Section 4. "Firmware" on page 16) provides support for USB-to-I2C bridging, allowing control of I2C devices via USB.
Note: It is recommended to connect AVSS0/1, SGND and VSS. In certain applications, however, it may be better to split signal ground from the other grounds in order to reduce noise.
2.9.2. I2C Slave In I2C slave mode, the interface provides an interrupt to the microcontroller after detecting the assigned I2C address (0x48). The corresponding interrupt service routine handles this request and interprets incoming data according to the application. One example of handling could provide full access to all memory locations.
Five-Volt Mode If a higher output level is required, the IC can operate in 5 V mode. In this case, the IC is powered from an external 5 V supply: AVDD has to be connected to AREG0 and AREG1 and SREF must be switched to 5 V mode.
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2.10. Analog Output Pins: OUTL, OUTR, FOPL, FOPR, FOUTL, FOUTR, FINL, FINR The analog output system comprises the stereo audio DAC, analog filters, op amps for external out-of-bandnoise filters, analog volume, mute, and the output amplifiers. 2.10.4.Line-out/Headphone Amplifier Pins: OUTL, OUTR
DATA SHEET
Stereo Mode The line-out/headphone amplifier output is provided at the OUTL and OUTR pins connected either to stereo headphones or to a power amplifier. The stereo headphones require external serial resistors in both channels. See Section 4. "Firmware" on page 16.
2.10.1. Digital-to-Analog Converters The UAC 3553B uses two multibit sigma delta DACs with high linearity and SNR better than 95 dBA.
OUTL
2.10.2. Analog Filter AVSS Pins: FOPL, FOPR, FOUTL, FOUTR, FINL, FINR This block contains the op-amps for the optional analog external out-of-band-noise filters. It is recommended to use a second-order filter for the main channels (OUTL, OUTR) (see Section 4. "Firmware" on page 16). It is possible to omit these filters and to save the external components. In this case, the op-amp has to be switched off and the pins FOOTL/R, FINL/R and FOPL/R must be connected. The output signal will contain more out-of-band noise, which is not audible, however. OUTR
AVSS Fig. 2-5: Loudspeaker connection for stereo mode
Mono Mode In Mono mode, the DC coupling capacitors and further filter circuitry are not required. In this mode, the output pins OUTL/R operate in bridge mode with complementary signals. Therefore, the maximum output power increases allowing small speakers to be driven directly.
2.10.3. Analog Volume The analog volume covers a range from +6 dB to 18 dB with 1.5 dB step size. But this is the analog component of the overall volume system which covers a range from +12 dB to -114 dB with 1 dB step size and additional mute position. It is split into analog and digital volume. This splitting ensures that the DAC performance parameters do not degrade at reduced volume settings. The splitting is embedded in the audio processing and cannot be modified.
OUTR
OUTL Fig. 2-6: Loudspeaker connection for mono mode
Note: Positive volumes will degrade the THD at high input levels.
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2.11.Special I/O Table 2-3: SUSPEND pin Pins: SOF, SEN, SUSPEND, RESET The following sections describe some pins with special functions. SUSPEND high low 2.11.1.SOF (Start of Frame) The SOF pin provides a 1 ms periodic signal which is derived from the USB frame rate. It can be used for test purposes or as an USB-synchronous reference for vendor-specific external circuitry. 2.11.4. Reset Pin: RES The RES pin resets the UAC 3553B. During power up the RES pin should be low until the clock system is up and running. Then this pin can be released and the UAC 3553B enters normal operating mode. normal power low power
2.11.2.SEN (Suspend Enable) Pin: SEN This is a digital input that prevents the device from entering the low-power mode (Suspend). The UAC 3553B enters a low-power mode if: - J-state on D+, D- lines (USB-Suspend) and Vbus high - Vbus low (USB-disconnected)
Note: In low-power mode, the RES pin must not be low, to avoid restart of the clock system and thus entrance to normal power mode.
90%
Note: Both cases must be supported by the firmware
AVDD VDD
In the case of USB-Suspend, the SEN pin is also used as an input for the remote wake-up function. RES Table 2-2: SEN pin SEN high low suspend enabled suspend disabled/remote wake-up 2.12.Clock System Pins: XTI, XTO The UAC 3553B requires a 12 MHz clock source, which is implemented as an on-chip oscillator with external crystal. Also an external oscillator can be used. In this case, the clock has to be connected to XTI (see also Section 4. "Firmware" on page 16). The 12 MHz is the input clock for a PLL circuit which generates all clocks required within the IC. The clock for the APU is programmable either to 48 MHz or 72 MHz. With 48 kHz, the UAC 3553B consumes less power, but on the other hand a reduced feature set for the audio processing has to be taken into account (see Fig. 3. on page 12). Fig. 2-7: Timing diagram of the reset procedure
20 ms
2.11.3. Suspend Pin: SUSPEND The SUSPEND pin is a digital output pin which indicates the low-power mode. It can be used to power down external circuitry, like power amplifiers in a USB speaker.
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3. Audio Processing
(downstream)
mix
AGC
Treble/ Loudness
EQ
Complementary High Pass
Balance
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dashed blocks not available in reduced feature set
USB
USB
Bass/
Mono/ Stereo + Right Invert
D
Vol.
A D A
L
R
I2S
Low Pass Q-Peak
MB
I
2S
mix
Fig. 3-1: Signal flow in the audio processing unit (APU)
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UAC 3553B
The audio processing is implemented by the APU firmware. The audio building blocks can be split into USBindependent features such as parametric equalizer, I2S I/O, and blocks which belong to USB feature units, mixer units, and selection units defined in the USB Device Class Definition for Audio Devices. The USB feature unit provides basic manipulation of the incoming logical channels and can be controlled by the standard OS-provided mixer tool. The parameters for the USB-independent features are predefined in the internal ROM, in an external EEPROM or a special host application which drives the IC. The UAC 3553B supports two logical channels (i.e., left and right). Multichannel or surround systems, however, can also be realized using more than one UAC 3553B, because phase or delay distortion is eliminated in the device by locking the audio processing to the USB frame rate. An overview of the architecture is given in Fig. 3-1 on page 12. If the APU works with a 48 MHz clock, it is necessary to select the reduced feature mode. Those blocks not available in reduced feature mode, are shown with dashed lines in Fig. 3-1 on page 12.
Table 3-1: AGC parameters Parameter Decay time Settings 8s 4s 2s 20 ms Default 4 seconds
Output Level dBr
-9 -15 -21
AGC off AGC on
-30
-24
-18
-12
-6
0
+6 dBr Input Level
Fig. 3-2: Simplified AGC characteristics 3.1. Sample Rate Converters The tasks for the sample rate converters are: - to transform the block-transferred audio on the USB bus into a continuous data stream and vice versa, - to convert all incoming and outgoing sample rates to and from a fixed 48 kHz sample rate. This technique eliminates input and output data jitter. Furthermore, all audio algorithms, the ADCs, and the DACs run on a single sample rate and no parameter switching is required on change of audio sampling rate. The sample rate converters support input and output sampling rates from 6.4 kHz up to 48 kHz. 3.3. Quasi-Peak A quasi-peak detector is provided in the DAC channel. This can be used, e.g., for a VU-meter on the host side. The feature is based on using the following fast attack and slow decay time constants: attack time: 1.3 ms decay time: 37 ms
3.4. Bass Control 3.2. Automatic Gain Control The Automatic Gain Control (AGC) is one of the building blocks of the feature unit (USB Device Class Definition for Audio Devices 1.0, page 39). Different sound sources fairly often do not have the same volume level. The Automatic Gain Control solves this problem by equalizing the volume levels within a defined range. Below a threshold level the signals are not affected. The level-adjustment is performed with time constants in order to avoid short-time adjustments due to signal peaks. The bass control provides gain or attenuation to frequency components below a cut-off frequency of 120 Hz. The bass control works identically on both channels in a range of -12 dB to +12 dB.
3.5. Treble Control The treble control provides gain or attenuation to frequency components above a cut-off frequency of 6 kHz. The treble control works identically on both channels in a range from -12 dB to +12 dB.
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3.6. Parametric Equalizer The parametric equalizer is an audio feature which is not accessed via standard USB controls. It allows the compensation of the frequency response of a speaker. Alternatively, frequency responses can be set to suit individual tastes. The equalizer consists of five individually adjustable bands. The control parameters and the parameter range for each band is shown in Table 3-2. Table 3-2: Equalizer parameters Parameter Center Frequency Gain/Attenuation Filter Quality (Q) Min. 50 Hz -6 dB 0.5 Max. 15 kHz +6 dB 3 Table 3-3: MB parameters Parameter Effect Strength Harmonic Content Center Frequency Amplitude Limit Range off to max. 0 to 100% 20 to 300 Hz -32 to 0 dBFS 3.8. Micronas Bass (MB)
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The Micronas bass algorithm (MB) implements a sophisticated bass boost system, which extends the frequency range of loudspeakers or headphones. The MB is placed in the crossover filter path. The enhanced bass signal can be added back onto the left/ right channels. Micronas bass combines two effects: dynamic amplification and adding harmonics. Several parameters allow tuning the characteristics of MB according to the loudspeaker, the cabinet, and personal preferences. For more detailed information on how to set up MB, Micronas provides an appropriate Application Note.
Default if disabled off 0% 90 Hz 0 dBFS (= no limit)
Default if enabled medium 50% 90 Hz 0 dBFS (= no limit)
The adjustment of the equalizer is supported by an application program that allows setting up frequency responses and downloading the corresponding filter coefficients into the UAC 3553B. When the frequency response matches the requirements, it can be programmed into the external EEPROM or can be set by a vendor-specific device driver. The UAC 3553B is shipped with a flat frequency response.
3.7. Volume, Mute, and Balance Control The volume control is partly implemented in the analog back-end. This preserves high audio quality (SNR) at low volume settings because signal and noise are attenuated in the same way. This is a significant advantage over digital-only implementations since it preserves the native audio bit resolution in the processing path. The UAC 3553B uses digital volume control only for the fine stepping. The volume setting is smoothed by an internal ramping algorithm in order to avoid audible clicks during volume change. The splitting between analog and digital volume is handled by the UAC 3553B automatically. The balance is implemented digitally by attenuating one channel. The mute control is part of the volume system in the UAC 3553B. It functions simultaneously on both channels and can be switched on and off under USB control. Similar to the volume control, clicks are avoided by a ramping algorithm.
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3.8.2. Adding Harmonics MB exploits the psychoacoustic phenomenon of the `missing fundamental'. Adding harmonics of the frequency components below the cut-off frequency gives the impression of actually hearing the low-frequency fundamentals. In other words: Although the loudspeaker system is not capable of generating such low frequencies, the listener has the impression that it reproduces them.
3.8.1. Dynamic Amplification Since the human impression of loudness depends on the frequency, a dynamic compression of the low frequencies adapts the sound to the human perception. In order to prevent clipping, and to adapt the system to the signal amplitude which is really present at the output of the device, the MB contains a definable limit. The output signal amplitude is monitored and if it comes close to the limit, the gain is reduced automatically. Clipping effects are avoided.
Signal Level
MB_LIMIT
Amplitude (db)
Amplitude (db)
Frequency MB_CF Frequency MB_CF SUBW_FREQ
Fig. 3-4: Adding harmonics
Fig. 3-3: Dynamic amplification
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4. Firmware It was the purpose of the previous chapters to describe the UAC 3553B from the hardware point of view. The complete functionality, however, is defined by the microcontroller firmware. This firmware tailors the device to a specific application. Micronas offers a standard DAC firmware version which is embedded in the ROM. 4.1.1. Device Descriptor
DATA SHEET
The device descriptor contains the downloadable IDs and the index for the strings. Table 4-1: Programmable device descriptor items Item idVendor Default - UAC 3553B 0x074D 0x3553 0x000x1) 0x01 0x02 0x00
Note: By means of an external EEPROM, it is possible to customize many parameters (IDs, strings, equalizer setting etc.).
idProduct bcdDevice iManufacturer
4.1. Features The main features of the standard firmware versions are - USB playback with sample rates from 6.4 kHz to 48 kHz - Audio baseband processing including dynamic bass management - Basic audio control by GPIO-HID - Suspend mode and remote wake-up support - IC master/slave support - bootloader allows download of configuration data, plug-ins after power-on - plug-in support (downloadable firmware extensions from external EEPROM or WIN driver) Most of the functionality is defined in the device and configuration descriptor. The following chapters provide all noteworthy information buried in this descriptor. It is assumed that the reader is familiar with the basic USB notation (USB Spec 1.1 etc.).
iProduct iSerialNumber
1)
changes with new firmware revisions
Associated to the string index there are three programmable strings. The ROM firmware defines only two: Table 4-2: Strings used in DAC firmware String Manufacturer String Product String Default - UAC3553B Micronas UAC3553B USB-DAC
4.1.2. Configuration Descriptor First the configuration descriptor contains information on the bus/self-powered and remote wake-up capabilities. The UAC 3553B allows all combinations of these features. There is also a string index, allowing to associate a string to this configuration. The default string is the date code (time of code assembly). These items are programmable. Table 4-3: Programmable configuration descriptor Items Item iConfig bmAttributes MaxPower Default - UAC3553B 0x01 0xC0 (self-powered, remote wake-up 0x00 (0mA)
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Then the configuration descriptor provides all information concerning the audio flow in the Class Specific Audio Control Interface. Fig. 4-1 shows the graphical representation for the DAC firmware. This is the audio structure as it appears to the USB host. Without any additional drivers, the Windows OS provides sliders in the mixing tool to control volume, bass, treble setting. Using a vendor-specific application, however, it is possible to extend this to the full signal routing capabilities (see Section 3. on page 12). This can be achieved by plug-ins from external EEPROM or Windows driver.
Table 4-5: Standard key configuration Pin GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Function Volume Up Volume Down Mute on-off toggle BassBoost on-off toggle Next Track Previous Track Stop Playback
Note: BassBoost enables a dynamic bass management algorithm with programmable (external EEPROM) characteristics.
The next part of the configuration descriptor defines the audio format for playback. This is not programmable. Table 4-4: Supported audio formats Playback Format 16-bit MONO 16-bit STEREO 24-bit STEREO
The keys are polled every 1 ms by the microcontroller and the corresponding key codes are transmitted to the host on request when a key enters high state. The host's polling rate is 8 ms. This parameter, however, is part of the configuration set, which can be downloaded from an external I2C EEPROM. If these HID functions are not required, the GPIO[0...7] can be used as general-purpose I/O by vendor-specific applications.
4.1.3. Audio Class Requests The UAC 3553B accepts all sample rates from 6.4 kHz to 48 kHz The last part of the configuration descriptor defines the HID functions: The DAC firmware uses the GPIO pins to connect keys which are related to the USB HID class. The standard configuration defines the GPIO0...GPIO7 as input pins for the audio and media control shown in Table 4-5. The DAC firmware supports all audio class requests which are required by the standard audio flow shown in Fig. 3-1. The MIN/MAX/RES setting follows the limits which are defined in the audio processing, apart from the main volume setting (FU1). In this case, the overall range from -114 dB to +6 dB is limited to -40 dB to +3 dB (plus mute position) in order to fit the audible range to the volume slider in the Windows mixer.
EP1
Volume,Mute, Bass,Treble BassBoost AGC IT FU ID1
Playback
OT ID14
USB
D/A
ID12
Fig. 4-1: Standard DAC audio flow
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4.2. Vendor-Specific Requests These requests provide functionality which extends standard controlling of the operating system. Micronas provides a driver for the Windows operating system which supports: - SET MEM This request allows writing all RAM and register locations in the chip. - GET MEM This request allows reading all memory locations in the chip. Block read is supported. - SET I C This vendor request allows to drive the I2C-master in the DAC firmware. It allows writing to external I2C devices. - GET I2C This request supports I2C master reading from external devices.
2
DATA SHEET
4.2.1. Bootloader The bootloader is a part of the firmware which allows communication with an external I2C EEPROM. In multimaster applications with I2C control, however, it is not allowed to have I2C traffic coming from UAC 3553B and therefore, the bootloader needs to be enabled by GPIO7: Table 4-6: Bootloader enable Setting GPIO7 = 0 GPIO7 = 1 Bootloader disabled enabled
The bootloader runs immediately after power-on. At this moment, the device is not connected to the USB bus. When the bootloader has finished, the pull-up resistor is switched on the D+ line to signal to the host that the device is ready for enumeration. If no external EEPROM is found, the UAC 3553B continues with the default configuration. Two I2C EEPROM types with different I2C device IDs and number of subaddresses are supported and can be selected by GPIO6. The EEPROM type and size must be chosen according to the content. Table 4-7: Supported I2C EEPROM types
GPIO6 1 Device ID 0x51 Subaddresses 1 Byte Size <2 kbit Purpose Configuration (and very small plugins) Configuration and plug-ins
0
0x50
2 Bytes
>2 kbit
The size of the EEPROM must be chosen according to the content. Details on the EEPROM content and the structure of the different sections can be found in separate application notes. Using GPIO6/7 as bootloader option bits may cause conflicts with the use of these pins as HID media control pins. In this case, a plug-in or a hardware workaround is available.
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DATA SHEET
UAC 3553B
5. Specifications 5.1. Outline Dimensions
Fig. 5-1: PMQFP44-1: Plastic Metric Quad Flat Package, 44 leads, 10 x 10 x 2 mm3 Ordering code: QG Weight approximately 0.5 g
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UAC 3553B
5.2. Pin Connections and Short Descriptions NC = not connected, leave vacant LV = if not used, leave vacant Pin No.
PMQFP 44-1
DATA SHEET
VSS = if not used, connect to VSS OBL = obligatory; connect as described in circuit diagram VDD = connect to VDD Connection
(If not used)
Pin Name
Type
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
XTI XTO AREG1 AVSS1/AVSS0 OUTL OUTR AREG0 AVDD DAI WSI CLI GPIO 7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0 SDA SCL TRDY VBUS VREG DMINUS DPLUS VSS VDD
IN OUT OUT IN OUT OUT OUT IN IN IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT IN OUT IN/OUT IN/OUT IN IN
OBL OBL OBL OBL LV LV OBL OBL VSS VSS VSS LV LV LV LV LV LV LV LV LV LV LV OBL OBL OBL OBL OBL OBL
Quartz Oscillator Pin 1 Quartz Oscillator Pin 2 Regulator Output for analog parts except amplifiers VSS for analog parts Audio Output: headphone left/speaker Left Audio Output: headphone right/speaker Right Regulator Output for audio output amplifiers analog VDD I2S Data Input I2S Word Strobe I2S Bit Clock HID IO 7 HID IO 6 HID IO 5 HID IO 4 HID IO 3 HID IO 2 HID IO 1 HID IO 0 I2C Data I2C Clock Test Output Pin Sense USB Bus Capacitor for internal supply USB DATA MINUS USB DATA PLUS Digital VSS Digital VDD
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DATA SHEET
UAC 3553B
Pin No.
PMQFP 44-1
Pin Name
Type
Connection
(If not used)
Short Description
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
TEST RES SUSPEND SOF SEN FOUTL FOPL FINL FOUTR FOPR FINR NC NC SGND SREF NC
IN IN OUT OUT IN OUT IN/OUT IN/OUT OUT IN/OUT IN/OUT
VSS VDD LV LV VSS OBL OBL OBL OBL OBL OBL LV LV
Test Enable Power On Reset, active low Low-Power Mode Indicator 1-ms Start-Of-Frame Signal Suspend Enable Output to left external filter Filter Op Amp Inverting Input, left Input for FiltoutL Output to right filter op amp Right Filter op amp inverting input Input for FILTOUTR Leave Vacant Leave Vacant Signal Reference Ground Signal Reference Voltage Leave Vacant
IN IN
OBL OBL LV
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UAC 3553B
5.3. Pin Descriptions 5.3.1. Power Supply Pins The UAC 3553B combines various analog and digital functions which may be used in different modes. For optimized performance, major parts have their own power supply pins. All VSS power supply pins must be connected. VDD (28) VSS (27) The VDD and VSS power supply pair are connected internally with all digital parts of the UAC 3553B. AVDD (8) AVDD is the supply pin for the voltage regulators at AREG0(9) and AREG1(4). AVSS0/1 (4) AVSS1 is the ground connection for the analog audio processing parts, including the headphone/loudspeaker amplifiers. SREF (43) Reference for analog audio signals. This pin is used as reference for the internal op amps. This pin must be blocked against SGND with a 3.3 F capacitor. 5.3.2. Analog Audio Pins FOUTL (34) FOPL (35) FINL (36) FOUTR (37) FOPR (38) FINR (39)
DATA SHEET
Filter op amps are provided in the analog baseband signal paths. These inverting op amps are freely accessible for external use by these pins. The FOUTL/R pins are connected with the buffered output of the internal switch matrix. The FOPL/R pins are directly connected with the inputs of the inverting filter op amps. The FINL/R pins are connected to the outputs of the op amps. OUTL (5) OUTR (6) These pins are connected to the internal output amplifiers. OUTL/R can be used for either line-out or stereo headphones.
Note: Warning: A short-circuit at these pins for more than a momentary period may result in destruction of the internal circuits!
Note: The pin has a typical DC level of 1.725 V. It can be used as reference input for external op amps when no current load is applied.
SGND (42) Reference ground for the internal band-gap and biasing circuits. This pin should be connected to a clean ground potential! Any external distortions on this pin will affect the analog performance of the UAC 3553B. AREG0 (7) Voltage regulator output for headphone/loudspeaker amplifiers supply. Connect an external ceramic capacitor to stabilize the regulator output. AREG1 (3) Voltage regulator output for analog audio processing parts supply, except the headphone/loudspeaker amplifiers. Connect an external ceramic capacitor to stabilize the regulator output.
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DATA SHEET
UAC 3553B
5.3.4. Other Pins XTI (1) XTO (2) The XTI pin is connected to the input of the internal crystal oscillator; the XTO pin to its output. Both pins should be directly connected to the crystal and two ground-connected capacitors (see application diagram).
5.3.3. Interface Pins DMINUS (25) DPLUS (26) Differential USB port pins. The DPLUS pin has an internal switchable pull-up resistor. Both pins must be connected to the USB bus via a series resistor. VBUS (23) Sense USB Bus. CLI (11) Clock line for the I2S bus. This line is driven by the UAC 3553B; in slave mode, an external I2S clock has to be supplied. DAI (9) Input of digital serial sound data to the UAC 3553B via I2S bus. WSI (10) Word strobe line for the I2S bus. In master mode, this line is driven by the UAC 3553B; in slave mode, an external I2S word strobe has to be supplied. SDA (20) Via this pin, the I2C bus data is written to or read from the UAC 3553B. SCL(21) Via this pin, the I2C bus clock signal has to be supplied.
Note: Do not drive external clock circuits via XTI/XTO!
SEN (33) Digital input that prevents the device from entering the low-power mode. This pin is also used to signal remote wake-up. TEST (29) Test enable. This pin is for test purposes only and must always be connected to VSS. VREG (24) Voltage regulator output for USB transceiver supply. Connect an external ceramic capacitor to stabilize the regulator output. RES (30) A LOW signal at this pin resets the chip. GPIO 0...7 (19, 18, 17, 16, 15, 14, 13, 12) These pins are configurable to either being input or output and can be used to connect audio function keys or signalling LEDs. SUSPEND (31) This pin indicates that the host PC sets the USB bus to the suspend mode state. SOF(32) Start of Frame Signal. 1 ms signal that can be used for external application circuits. TRDY (22) Test Output Pin. This pin is intended for test purposes only and must not be connected.
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UAC 3553B
5.4. Pin Configuration
DATA SHEET
VDD TEST RES SUSPEND SOF SEN VSS DPLUS DMINUS VREG VBUS
33 32 31 30 29 28 27 26 25 24 23 FOUTL FOPL FINL FOUTR FOPR FINR NC NC SGND SREF NC 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 TRDY SCL SDA GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7
UAC 3553B
17 16 15 14 13 12
XTI XTO AREG1 AVSS1/AVSS0 OUTL OUTR DAI AVDD AREG0 WSI
CLI
Fig. 5-2: PMQFP44-1 package
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DATA SHEET
UAC 3553B
5.5. Pin Circuits AREG1 ext. filter network XTI FOUTn FOPn FINn P N
Enable
P P XTO N N
SREF Fig. 5-3: Pins FINR, FOPR, FINL, FOPL AVSS0/1 Fig. 5-6: Clock oscillator XTI, XTO SREF
115 k
SGND Fig. 5-4: Pins SREF, SGND
Fig. 5-7: Input pins RES, TEST, SEN, DAI
FOUTn SREF SREF
OUTn
Fig. 5-8: Output pins OUTL, OUTR Fig. 5-5: Output pins FOUTL, FOUTR
DVSUP P N GND Fig. 5-9: Digital output pins SOF, SUSPEND, TRDY
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UAC 3553B
DATA SHEET
VREG P
1.5 k
AVDD VREG -
+
DPLUS
AREG0/1
DMINUS VSS
Suspend
AVSS0/1 Fig. 5-14: Analog voltage supply pins AVDD, AVSS, AREG0/1 Fig. 5-10: Digital input/output pins DMINUS, DPLUS, VREG VDD -
+
DVSUP P N GND Fig. 5-11: Input/output pins GPIO0...GPIO7, WSI, CLI VSS
VREG
Fig. 5-15: Digital voltage supply pins VDD, VSS, VREG
Fig. 5-12: Input pin VBUS
N GND Fig. 5-13: Input/output pins SDA, SCL
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DATA SHEET
UAC 3553B
5.6. Electrical Characteristics Abbreviations: tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip
5.6.1. Absolute Maximum Ratings Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. All voltages listed are referenced to ground (VSUPA, VSUPDx = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power up/down sequences, see the instructions in Section 2.8. of this document. Symbol Parameter Pin Name Min. TA TC TS PMAX VSUPA VSUPA VSUPDx VGRND Ambient Operating Temperature Case Operating Temperature PMQFP44-1 Storage Temperature Power Dissipation PMQFP44-1 Analog Supply Voltage 1) Analog Supply Voltage 2) Digital Supply Voltage Voltage Differences between different Grounds Input Voltage, all digital inputs Input Current, all digital inputs Output Current, all digital outputs Input Voltage, all analog inputs Input Current, all analog inputs AVDD AVDD, AREG0/1 VDD AVSS0, AVSS1, VSS -10 -10 -40 - -0.3 -0.3 -0.3 -0.5 Limit Values Max. 70 1153) 125 7603) 6 6 6 +0.5 C C C mW V V V V Unit
VIdig IIdig IOdig VIana IIana
1) 2) 3)
-0.3 -20 -50 -0.3 -5
VSUPD + 0.3 +20 +50 VVAREG0/1+ 0.3 +5
V mA mA V mA
Internal regulators used If internal regulators are not used, connect AVDD to AREG0/1. Package limit.
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UAC 3553B
DATA SHEET
Symbol
Parameter
Pin Name Min. OUTL/R AREG0 AREG1 -0.2 -500 -50
Limit Values Max. 0.2 +20 +20
Unit
IOaudio IAREG0 IAREG1
1)
Output Current, audio output1) Output Current, analog regulator Output Current, analog regulator
A mA mA
These pins are not short-circuit proof!
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DATA SHEET
UAC 3553B
5.6.2. Recommended Operating Conditions Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. All voltages listed are referenced to ground (VSUPA, VSUPDx = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power up/down sequences, see the instructions in section Section 2.8. of this document. Symbol Parameter Pin Name Min. Temperature Ranges and Supply Voltages TA TC PMAX VSUPA CSUPA VSUPD CSUPD CSUPUSB Ambient Temperature Range Case Operating Temperature PMQFP44-1 Power Dissipation PMQFP44-1 Analog Audio Supply Voltage Capacitor at analog supply pins to ground Digital Supply Voltage Capacitor at digital supply pin to ground Capacitor at VBUS pin to ground AVDD AVDD VDD VDD VBUS 4.1 4.1 5.0 220 5.0 100 22 5.6 0 25 65 70 110 650 mW 5.6 C C C V nF V nF nF Limit Values Typ. Max. Unit
Analog Reference CSREF1 CSREF2 Analog Reference Capacitor Ceramic Capacitor in parallel SREF SREF 1 3.3 100 F nF
Analog Audio Filter Inputs and Outputs ZAFLO ZAFLI Analog Filter Load Output1) Analog Filter Load Input1) FOUTL/R FINL/R 7.5 6 5.0 7.5 Analog Audio Outputs ZAOL_HP
1)
k pF k pF
Output Load Headphone (16 series resistor required)
OUTL/R
16
32 100
pF
Please refer to Section 6. "UAC 3553B Applications" on page 38
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UAC 3553B
DATA SHEET
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Crystal Characteristics1) TAC FP VACLK F/Fs F/Fs REQ C0 PD Ambient Temperature Range Load Resonance Frequency at Cload = 15 pF2) Clock Amplitude Accuracy of Adjustment Frequency Variation versus Temperature Equivalent Series Resistance Shunt (parallel) Capacitance Drive Level 3 XTI XTI, XTO 0.5 -500 -500 0 12 VREG-0.5 500 500 60 5 1 70 C MHz VPP ppm ppm pF mW
1)
Voltage Regulator CVREG CAREG0 CAREG1 Transceiver RUSB
1) 2)
Voltage Regulator Capacitor (ceramic, X5R) Voltage Regulator Capacitor (ceramic, X5R) Voltage Regulator Capacitor (ceramic, X5R)
VREG AREG0 AREG1
330 330 150
1000 470 220 600 270
nF nF nF
Input Series Resistance
DPLUS/ DMINUS
24 (5%)
For device characteristics refer to page 31 Cload should typically be 15 pF (+30%/-10%), e.g., Y5U. Ref. to application circuit (see Fig. 6-2 on page 39)
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DATA SHEET
UAC 3553B
5.6.3. Characteristics At TA = 0 to 70 C, VSUPD = 4.1 V to 5.6 V, VSUPA = 4.1 V to 5.6 V. Typical values at TA = 20 C, VSUPD = VSUPA = 5.0 V, quartz frequency = 12 MHz, duty cycle = 50%, bass/treble: 0 dB, Micronas Bass: off, AGC: off, equalizer: off (positive current flowing into the IC), 3 V mode, reduced feature set, if not otherwise specified.
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
Symbol
IVDD
Parameter
Current Consumption
1)
Pin Name
VDD
Limit Values
57 45 30 70 80
Unit
mA A 72 MHz APU clock 48 MHz APU clock Suspend
Digital Input Pin II VIL VIH Input Leakage Current Input Low Voltage Input High Voltage GPIO[7:0], SEN, RES, VBUS, DAI, WSI, CLI
1
0.4
A
V V
VGND VI VSUP
-0.4V
VSUPD
Digital Output Pin VOH VOL IO_max Output High Voltage Output Low Voltage Max. Output Current GPIO[7:0], SUSPEND, SOF, WSI, CLI, SDA, SCL
-0.4
VSUPD 0.4 13) 82)3)
V V mA
Pins set to output Iout =8 mA
output set to "weak" output set to "strong"
Analog Supply IAVDD Current Consumption Analog Audio AVDD 12 120 25 15 135 mA A mA all analog blocks on, Mute Suspend RL 32 (external 16 series resistor required) Volume = 0 dB, Input signal 1kHz at 0 dBFS 1 kHz sine wave at 100 mVrms 100 kHz sine wave at 100 mVrms
PSRRAA
Power Supply Rejection Ratio for Analog Audio Outputs (internal regulators active)
AVDD, OUTL/R
95 55
dB dB
Analog Supply Voltage Regulators VAREG
1) 2) 3)
Output Voltage
AREG0/1, AVSS0/1
3.3
3.5
3.7
V
no load attached to GPIOs max output current for driving LEDs is 20 mA. the sum of these digital output pin currents must not exceed 100 mA. Higher currents might damage the device.
Please consider power limitations due to USB specification.
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UAC 3553B
DATA SHEET
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
Reference Frequency Generation VDCXTI CLI CLO VXTALOUT TOSC_rise DC Voltage at Oscillator Pins Input Capacitance at Oscillator Pin Input Capacitance at Oscillator Pin Voltage Swing at Oscillator Pins (peak-to-peak) Oscillator Start-Up Time XTI/O XTI XTO XTI/O 0.6 x VAreg1 0.5 x VAreg1 3 3 1.0 x VAreg1 10 V pF pF V ms after min. VSUPA is reached
USB Transceiver VREG RO Regulator Voltage Driver Output Resistance including the 24 external serial resistor Rise and Fall Times Rise/Fall Time Matching Crossover Voltage Differential Receiver Common-Mode Range Single-ended Receiver Threshold Voltage Switchable Pull-up Resistor VREG D+/D- 3.25 28 3.4 3.55 43 V CL=1 F static, LOW or HIGH
tr / tf MA_TRTF VXOVER VCM_DREC VT_SREC Rpu
D+/D- D+/D- D+/D- D+/D- D+/D- VREG, D+
4 90 1.3 0.8 0.8 1.5 1.65
20 110 2.0 2.5 2.0
ns % V V V k
CL=50 pF, driver mode CL=50 pF, driver mode CL=50 pF, driver mode
USB connected
Analog Audio VSREF VAO Signal Reference Voltage Analog Output Voltage AC SREF OUTL/R 1.6 1.725 2.4 1.8 V Vpp RL >> 10 M, referred to SGND BW = 20 Hz...22 kHz, RL 10k, volume = 0 dB, Input 1 kHz at 0 dBFS digital (I2S) volume = 0 dB 1 kHz sine wave at 100 mVrms 100 kHz sine wave at 100 mVrms 0...20 kHz (with 2nd order post filter) 31 kHz...164 kHz (with 2nd order post filter)
RinAO PSRRA0
Analog output resistance1) Power Supply Rejection Ratio
OUTL/R AVDD, OUTL/R AVDD, OUTL/R
3 881) 541) 0.11)
6
dB dB dB
RD/A
D/A Pass Band Ripple
OUTL/R
AD/A
D/A Stop Band Attenuation
401)
dB
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DATA SHEET
UAC 3553B
Symbol
Parameter
Pin Name Min.
Limit Values Typ. -90 Max. -85
Unit
Test Conditions
THDHP
Total Harmonic Distortion
OUTL/R
dB
BW = 20 Hz...22 kHz, RL 10k, Volume = 0 dB, Input 1 kHz at - 3 dBFS digital (I2S) BW = 20 Hz...22 kHz, unweighted, RL 32 , Volume = 0 dB, Input 1 kHz at -3 dBFS digital (I2S) BW = 20 Hz...22 kHz, Aweighted, RL 10k, Volume = 0 dB, Input 1 kHz at - 20 dBFS digital (I2S) BW = 20 Hz...22 kHz, Aweighted, RL 10k, Volume = -40 dB, Input 1 kHz at -3 dBFS digital (I2S)
THDHP
Total Harmonic Distortion
OUTL/R
-70
dB
SNRAO1
Signal-to-Noise Ratio2)
OUTL/R
90
97
dB(A)
SNRAO2
Signal-to-Noise Ratio2)
OUTL/R
95
102
dB(A)
USB Transceiver VREG RO Regulator Voltage Driver Output Resistance including the 24 external serial resistor Rise and Fall Times Rise/Fall Time Matching Crossover Voltage Differential Receiver Common-mode Range Single-ended Receiver Threshold Voltage Switchable Pull-up Resistor VREG D+/D- 3.25 28 3.4 3.55 43 V CL=1 F static, LOW or HIGH
tr / tf MA_TRTF VXOVER VCM_DREC VT_SREC Rpu
D+/D- D+/D- D+/D- D+/D- D+/D- VREG, D+
4 90 1.3 0.8 0.8 1.5 1.65
20 110 2.0 2.5 2.0
ns % V V V k
CL=50 pF, driver mode CL=50 pF, driver mode CL=50 pF, driver mode
USB connected
Analog Audio VSREF VAO Signal Reference Voltage Analog Output Voltage AC SREF OUTL/R 1.6 1.725 2.4 1.8 V Vpp RL >> 10 M, referred to SGND BW = 20 Hz...22 kHz, RL 10k, volume = 0 dB, Input 1 kHz at 0 dBFS digital (I2S) volume=0 dB 1 kHz sine wave at 100 mVrms 100 kHz sine wave at 100 mVrms
RinAO PSRRA0
Analog output resistance1) Power Supply Rejection Ratio
OUTL/R AVDD, OUTL/R AVDD, OUTL/R
3 881) 541)
6
dB dB
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UAC 3553B
DATA SHEET
Symbol
Parameter
Pin Name Min.
Limit Values Typ. 0.11) Max.
Unit
Test Conditions
RD/A
D/A Pass Band Ripple
OUTL/R
dB
0...20 kHz (with 2nd order post filter) 31 kHz...164 kHz (with 2nd order post filter) BW = 20 Hz...22 kHz, RL 10k, Volume = 0 dB, Input 1 kHz at - 3 dBFS digital (I2S) BW = 20 Hz...22 kHz, unweighted, RL 32 , Volume = 0 dB, Input 1 kHz at -3 dBFS digital (I2S) BW = 20 Hz...22 kHz, Aweighted, RL 10k, Volume = 0 dB, Input 1 kHz at - 20 dBFS digital (I2S) BW = 20 Hz...22 kHz, Aweighted, RL 10k, Volume = -40 dB, Input 1 kHz at -3 dBFS digital (I2S) BW = 20 Hz...22 kHz unweighted, no digital input signal, Volume = Mute RL = 32 , 16 series resistance, Volume = 0 dB, Input = 0 dBFS digital (I2S) RL = 16 , no series resistors, right channel inverted and output set to mono (bridge mode) Volume = 0 dB, Input = 0 dBFS digital (I2S)
AD/A
D/A Stop Band Attenuation
401)
dB
THDHP
Total Harmonic Distortion
OUTL/R
-90
-85
dB
THDHP
Total Harmonic Distortion
OUTL/R
-70
dB
SNRAO1
Signal-to-Noise Ratio2)
OUTL/R
90
97
dB(A)
SNRAO2
Signal-to-Noise Ratio2)
OUTL/R
95
102
dB(A)
LevMute
Mute Level L/R
OUTL/R
-110
dB
PHP
Output Power (Speaker/Headphone)
OUTL/R
10
mWeff
PHP
Output Power in Bridge Mode (Mono Speaker/Headphone)
OUTL/R
180
mWeff
VOLAO dVOLAO VOLGA VOLdGA XTALKHP
Output Volume Setting Range Output Volume Step Size Output Volume Error Analog Output Volume Step Size Error Crosstalk Left/Right Channel (Headphone)
OUTL/R OUTL/R OUTL/R OUTL/R OUTL/R
-90 1
0
dB dB
-0.5 -0.5
0 0
0.5 0.5 -80
dB dB dB RL = 32 , 3 V Mode, Volume = 0 dB, Input = -3 dBFS digital (I2S)
-95
1)
not tested in production
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DATA SHEET
UAC 3553B
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
Different Characteristics in Five-Volt Mode VSREF VAO Signal Reference Voltage Analog Output Voltage AC SREF OUTL/R 2.25 2.3 3.2 2.35 V Vpp RL >> 10 M, referred to SGND BW = 20 Hz...22 kHz, RL 10 k, volume = 0 dB, Input 1 kHz at -3 dBFS digital (I2S) BW = 20 Hz...22 kHz, RL 10k, Volume = 0 dB, Input 1 kHz at -3 dBFS digital (I2S) BW = 20 Hz...22 kHz, Aweighted, RL 10k, Volume = 0 dB, Input 1 kHz at - 20 dBFS digital (I2S) BW = 20 Hz...22 kHz, Aweighted, RL 10k, Volume = -40 dB, Input 1 kHz at -3 dBFS digital (I2S) RL = 32 , 16 series resistance, Volume = 0 dB, Input = 0 dBFS digital (I2S) RL = 16 , no series resistors, right channel inverted and output set to mono (bridge mode) Volume = 0 dB, Input = 0 dBFS digital (I2S)
THDHP
Total Harmonic Distortion
OUTL/R
-93
-85
dB
SNRAO1
Signal-to-Noise Ratio2)
OUTL/R
90
99
dB(A)
SNRAO2
Signal-to-Noise Ratio2)
OUTL/R
95
109
dB(A)
PHP
Output Power (Speaker/Headphone)
OUTL/R
17
mWeff
PHP
Output Power in Bridge Mode (Mono Speaker/Headphone)
OUTL/R
320
mWeff
2)
related to 0 dBFS input level
Different Characteristics for Full Feature Set (see Fig. 2-1 on page 6), Three-Volt Mode SNRAO1 Signal-to-Noise Ratio2) OUTL/R 88 95 dB(A) BW = 20 Hz...22 kHz, Aweighted, RL 10k, Volume = 0 dB, Input 1 kHz at - 20 dBFS digital (I2S) BW = 20 Hz...22 kHz, A-weighted, RL 10k, Volume = -40 dB, Input 1 kHz at -3 dBFS digital (I2S)
SNRAO2
Signal-to-Noise Ratio2)
OUTL/R
93
100
dB(A)
2)
related to 0 dBFS input level
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UAC 3553B
5.6.4. I2S Interface Timing Characteristics
Symbol ts_I2S th_I2S td_I2S to_I2S Parameter I2S Input Setup Time before Rising Edge of Clock I2S Input Hold Time after Rising Edge of Clock I2S Output Delay Time after Falling Edge of Clock I2S Output Setup Time before Rising Edge of Clock CLI WSI CLI 4 Pin Name CLI DAI Min. 10 40 30 Typ. Max. Unit ns ns ns ns
DATA SHEET
Test Conditions
CL=30 pF CL=30 pF
WSI - Input
SONY format PHILIPS format
SONY format PHILIPS format Detail C
CLI - Input Detail A DAI - Input
R LSB L MSB L LSB R MSB R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Detail C
CLI - Input
1/FCLI =325.5 ns
Detail D
CLI - Output
1/FCLI =325.5 ns
Detail A
CLI - Input
Ts_I2S Th_I2S
DAI - Input Ts_I2S Td_I2S
WSI as INPUT
WSI as OUTPUT
Fig. 5-16: Timing: asynchronous I2S input
36
Feb. 17, 2005; 6251-595-2DS
Micronas
DATA SHEET
UAC 3553B
1/FI2SWS WSI - Input
SONY format PHILIPS format Detail C CLI - Input Detail A DAI - Input
R LSB L MSB
SONY format PHILIPS format Detail B
L LSB R MSB
R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Detail B
CLI - Output
1/FCLI =325.5 ns
Detail C
CLI - Output
1/FCLI =325.5 ns
Detail A
CLI - Output
Ts_I2S Th_I2S
DAI - Input Ts_I2S Td_I2S To_I2S Td_I2S
WSI as OUTPUT
WSI as OUTPUT
Fig. 5-17: Timing: synchronous I2S input
Micronas
Feb. 17, 2005; 6251-595-2DS
37
UAC 3553B
6. UAC 3553B Applications 6.1. Recommended Low-Pass Filters for Analog Outputs
DATA SHEET
2nd-order
11 k 11 k
11 k 220 pF
1.0 nF
AVSS1
FOUTL(R)
FOPL(R)
FINL(R)
-
Fig. 6-1: 2nd-order low-pass filter
If the filter is not used, then FOUTL(R), FOPL(R), and FINL(R) are to be connected (dashed line) and the internal op-amp must be switched off. Table 6-1: Attenuation of second-order low-pass filter Frequency 24 kHz 30 kHz Gain -1.5 dB -3.0 dB
Note: First or third-order low-pass is also possible, but then the frequency response degrades.
6.2. External Clocking via XTI AC coupling of the clock signal The input level should be in the range between 0.5 and 2.5 VPP. for a load capacitance of 22 pF at XTO. DC coupling of the clock signal The DC input level must be 0.5 x VAREG1 which is typically 1.75 V. The input level should not exceed 0.5 to 2.5 VPP. See also Section 2.12. on page 11.
38
Feb. 17, 2005; 6251-595-2DS
Micronas
6.3. Typical Application
Micronas
Feb. 17, 2005; 6251-595-2DS
DATA SHEET
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39
UAC 3553B
7. Data Sheet History 1. Data Sheet: "UAC 3553B Universal Serial Bus", May 21, 2003, 6251-595-1DS. First release of the data sheet. 2. Data Sheet: "UAC 3553B Universal Serial Bus", Feb. 17, 2005, 6251-595-2DS. Second release of the data sheet. Major changes: - Section 3.1. on page 13 "Sample Rate Converters" was added.
DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-595-2DS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
40
Feb. 17, 2005; 6251-595-2DS
Micronas

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